In the prior art, the typical design of a matrix time slot interchange switch having rows and columns of switch nodes was to, as an example, and during a write operation, to write data to the traffic RAM in each of the nodes even though data would be read from only a small number of those nodes so as to be output from the switch array. As an example, in a non-blocking switch array with eight input leads and eight output leads (8.times.8), only one-eighth of the nodes could be engaged in data transfer at any instant. Although many prior art memory chips use the same amount of power whether or not they are receiving data, these memory types are very power hungry and dissipate a lot of heat to the environment. CMOS (complementary metal oxide semiconductor) memory chips are thus a preferred type of memory where power dissipation is a concern. CMOS chips not only dissipate (consume) power as a function of the voltage levels of the incoming data but also as a function of the internal capacitance of the data receiving portion of the chip and the frequency of the incoming data. Thus, a CMOS chip operates in a standby mode with very little internal consumption of power but causes the dissipation of relatively large amounts of power when receiving data. This power consumption increases proportionally with the frequency of data PG,3 transfer. Thus, in a CMOS environment using prior art design approaches for an 8.times.8 matrix, the other seven-eighths of the nodes not only are needlessly dissipating internal power while receiving data, but in addition, are loading down the data driver and thus, causing the data driver to dissipate needless power. The dissipation of the energy by the memory nodes not being used, limits the size or density of a matrix that can be used, and additionally, in many applications, causes needless additional energy to cool the environment surrounding the switch array in an attempt to keep it within design temperature parameters.
This problem is overcome by the present invention in one or both of two ways. The typical prior art design for each node within a switch array included a connect memory storage means which typically was serially addressed in a manner similar to the addressing of the traffic memory in the write mode. The connect memory was loaded with an indirect address defining the physical location in the traffic memory that data was to be read from during a data output read operation. The memory location into which this indirect address is loaded corresponds in time of access to the time slot that the data is to appear on the output bus. This memory location also contained a read enable bit so only one node outputs data to each output bus at a given time. If more than one node were to attempt to write to a bus, corruption of the data would occur due to conflicting logic levels. The present invention adds extra memory storage space to the connect memory for containing write enable bits which are utilized to enable further switches which activate the traffic memory only during those times that it is needed to write data which will be output by that node. These write enable bits, for a given piece of data, are typically stored in a different connect memory location corresponding in access time to the value of the indirect address. The design of the present switch incorporated a device driver for use in write operations as a part of each node. Thus, these same write enable bits, used to cause the reactivation of the memory chip, also unload any connected data drivers. If the chip design is such that deactivation of the memory does not automatically unload any connected data drivers, the same write enable bit may be used to operate further switches which will electrically disconnect the traffic memory from incoming data lines except when needed for a write operation.
The correct position (location) to store the write enable bit in connect memory can be deduced either using software or hardware from the value of the data used in the indirect addressing scheme of the prior art. The read enable bit is, as mentioned, and as was typically the case in the prior art, merely placed in the same or a comparable memory location to the indirect addressing data bit(s).
The present invention saves power by preventing logic bit value changes in the traffic memory except when a read or write operation is required for transferring data through that node and thereby reducing power consumption for the read operation, the write operation, and additionally disconnects the driver to reduce power consumption by the data driver. While the preferred arrangement shown provides a very large reduction in power dissipation, even implementing one of the write enable or device driver deactivation functions will still produce substantial power savings.
It is thus an object of the present invention to improve the power efficiency of a matrix switch array.